1. Field of the Invention
This invention relates to a process of fabricating the insulated-gate field effect transistor (referred to as IGFET hereinafter), and more particularly to a process of fabricating a high power IGFET with a silicon gate electrode, and with a drain electrode formed on the undersurface of the semiconductor substrate.
2. Description of the Related Art
An IGFET which is constructed of source and channel regions at one surface, a silicon gate electrode on the surface, and a drain electrode on the other surface of a semiconductor substrate, thereby electric charges moving from the surface to the undersurface and being output from the drain electrode on it, is adapted for high breakdown voltage and high power application. Furthermore it is possible to form self-aligned channel regions of a prescribed short channel length using the silicon gate electrode as a part of diffusion mask by double diffusion technique involving introduction of p- and n-type impurities in sequence.
Such a process of fabricating the IGFET is disclosed, for example, in U.S. Pat. No. 4,953,302, which comprises forming p-type base regions by ion-implantation of boron atoms into an n-type semiconductor layer using exposed polycrystalline silicon gate electrode as a mask, followed by thermal treatment for annealing, and subsequently forming n-type source regions in those p-type base regions by thermal diffusion of phosphorus likewise using as a mask the polycrystalline silicon gate electrode left exposed, thereby channel regions being defined. This process can provide an n-channel type IGFET containing self-aligned channel regions formed in the p-type base regions at the substrate surface under the utilization of the difference in lateral diffusion between boron and phosphorus.
In the process described above, the polycrystalline silicon gate electrode, into which the p-type impurity is introduced during formation of the p-type base regions and the n-type impurity during formation of the n-type source regions, consequently both conductivity types of impurities counteracting against each other, results in creating an increased resistance. This produces a problem of increasing gate input resistance and in turn slowing down the switching speed of the IGFET.